Communication has come over a long way and from a period of time. From the period of how to communicate we have evolved to the stage of how to communicate effectively. Now an effective communication also implies to the quality of the received message by the receiver. This is where Digital Signal Processing (DSP) comes into play. DSP involves the sampling, filtering and presentation of the received signals so that a receiver can receive it in the best presentable form. The DSP circuits have also evolved themselves over a long period of time. These circuits, which are VLSI based, have high-speed capability but there is always an effort to response of these circuits. FPGA is one such effort in this direction. A field-programmable gate array (FPGA) is an integrated circuit (IC) that can be programmed in the field after manufacture. FPGAs are similar in principle to, but have vastly wider potential application than, programmable read-only memory (PROM) chips. FPGAs are used by engineers in the design of specialized ICs that can later be produced hard-wired in large quantities for distribution to computer manufacturers and end users. Ultimately, FPGAs might allow computer users to tailor microprocessors to meet their own individual needs. Field programmable gate arrays (FPGAs) now possess sufficient performance and logic capacity to implement a number of digital signal processing (DSP) algorithms effectively
Overview of the FPGA
There are four main categories of FPGA s currently commonly available: symmetrical array, hierarchical PLD, and sea of gates. In all of these FPGAs the interconnections and how they are programmed array. Currently there are four technologies in use. They are: static RAM cells, anti-fuse, EPROM transistor, and EEROM transistor. Depending upon the application, one FPGA technology may have feature desirable for the application.
SRAM cells control static RAM Technology—in the static RAM FPGA programmable connections are made using pass transistor, transmission gates, or multiplexers that. The advantages of this technology is that it allows fast in –circuit re configuration. The major disadvantage is the size of the chip required by the RAM technology.
Anti-Fuse Technology—An anti fuse recides in a high impedance state; and can be programmed into low impedance or “fused” state. A less expensive than the RAM technology, this device is program one device. EPROM/EROM Technology—This method is same as used in the EPROM memories. One advantage of this technology that it can be reprogrammed without external storage of configuration; though the EPROM transistors cannot be re-programmed in circuit. The following table shows some of the characteristics of the above programming technologies.
Characteristics of the FPGA Technology
Digital Signal Processing:
To perform the processing of the signal digitally, there is a need of interfacing between the analog signal and the digital processor. The interface is called an analog to digital (A/D) converter. The output of the A/D converter is a digital signal that is appropriate as an input to digital processor. The digital signal processor may be a large programmable digital computer or a small microprocessor programmed to perform the desired operation on the input signal. It may also be a hardwired digital processor configured to perform a specified set of operations on the input signals. programmable machines provides the flexibity to change the signal processing operation through a change in the software, whereas hardwired machines are difficult to reconfigure. Consequently, programmable signal processors are in vary common use. On the other hand, when signal-processing operations are well defined, a hardwired implementation of the operations can be optimized, resulting in a cheaper signal processor and, usually, one that runs faster than its programmable counterpart. In application where the digital o/p from the digital signal processor is to be given via another interface from the digital domain to the analog domain. Such an interface is called digital to analog (D/A) converter. Thus, the signal is provided to the user in the analog form. However, there are other practical applications involving signal analysis, where the desired information is converted in digital form and no D/A converter is needed.
Approach to Design:
Recent developments in the simulation capabilities of high level mathematical modeling tools have opened exciting new design flow possibilities. System level support for bit true modeling enables a designer to use a single environment to create floating and fixed point mode1, and to make scaling and rounding decisions early in the design process. At the same time, FPGA vendors have expanded commercial IP offerings to incorporate higher-level DSP functions. Together, these technologies enable a new flow for data path design that includes design iterations at the system level. In the past, DSP FPGA design required the combined efforts of a DSP engineer and a hardware engineer familiar with HDL or schematic based design. In this workshop we present a new method to derive an HDL netlist for a data path directly from a system level tool. The steps include construction of an ideal mathematical model, investigation of implementation effects, test bench creation, and hardware netlist generation. Traditional HDL design methods are then used to complete the design implementation. These concepts are illustrated through examples of digital filter realizations, Discrete Wavelet Transforms (DWT), and digital communications applications. Field programmable gate arrays (FPGAs) now possess sufficient performance and logic capacity to implement a number of digital signal processing (DSP) algorithms effectively.
It can be demonstrated that DSP algorithms can be implemented in an FPGA with levels of performance unattainable using a traditional single-chip processor. Exploiting parallelism as well as mapping techniques such as distributed arithmetic accomplishes this. For example, a tunable band-pass filter operating at a sample rate of 120MHz, which uses a single Xilinx XCV600 device to deliver 2.61 x109 multiply-accumulate operations per second.
High performance FPGA circuits are often achieved using design techniques generally Unfamiliar to the DSP design community, which traditionally relies on the processor to Implement DSP systems. In reviewing the evolution of DSP processors, Auckland and D’Arcy observed, “What is required is a combination of efficient DSP hardware (Capable of exploiting much of the available parallelism in the application) together with smart compiler technology”. If one finds shortcomings in tools for designing with DSP processors, which take advantage of familiar design techniques, developed for the general purpose processor market, problems with tools that target FPGA logic will only be more acute.
The present research seeks to provide to the DSP system architect a design environment and flow that is familiar and easy to use, yet targets FPGA hardware directly The key Design goals for the project are to:
- Provide DSP system modeling capability at a high level of abstraction, with simple operators such as delay, addition and multiplication, as well as FIR and IIR filters FFTs, and Discrete Wavelet Transforms
- Ensure that the same model can be used throughout the design process, from performing initial theoretical design to quantizing coefficients or selecting data word lengths.
- Generate an FPGA implementation of the datapath from the system model automatically, without requiring the addition of device-specific information.
- Support the task of synthesizing control logic for the FPGA implementation.Automate the creation of test benches for performing logic simulation on the final FPGA implementation.
Description of the design flow:
Working in Simulink, the DSP system designer creates a model of the hardware system as well as one or more test environments in which to simulate the model. The elements used in constructing the system model are all capable of operating on real (double precision, floating point) or integer (quantized, fixed-point binary) data types. When the model is first entered, simulation is typically performed using floating data types to verify that its theoretical performance is as desired. The internal data types are then converted to the bit true representations that will be used in the hardware implementation, and the model is re-simulated to verify its performance with quantized coefficient values and limited data bit widths, which can lead to overflow, saturation and scaling problems. User defined black boxes can also be incorporated in the modeling and elaboration process.
When the model has been converted to a form realizable in the FPGA and its performance meets specification; the designer can invoke the netlister and the test bench generator. The netlister extracts a hierarchical representation of the model’s structure annotated with all the element parameters and signal data types. A mapper then analyzes the elements in the hierarchy and creates a VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) description of the design. Where possible, the mapper uses the Xilinx CORE Generator™ to make hardware macros for specific design elements. When an element or its parameter values imply functionality unavailable in CORE Generator, the mapper instantiates a reference to a parameterized, synthesizable entity in a synthesis library or user supplied model. The actual hardware entities used have additional inputs and outputs for control signals that are not evident at the level of abstraction used in Simulink. The mapper inserts the necessary control ports and connects them up to control logic blocks. Multi-rate clocking can be supported through time step information provided during simulation.Each control logic block is given a default synthesizable behavior which may require alteration by a logic designer to achieve a working implementation. This manual intervention in the back end is shown in the flow as the block labeled Control Design.
The test bench generator is an interactive tool that runs in the Matlab environment, in which the designer captures the input stimuli and system outputs of selected simulation runs for conversion to test vectors. The generator converts the captured simulation data into VHDL code that will exercise the implemented model and test its outputs against the expected results.
The Xilinx Foundation Series tools are used to synthesize the control logic and those elements for which no hardware macros exist and combine all the pieces into a single fully-realized netlist, and place and route the design in an FPGA. The outputs of this back-end process are a bit-stream (FPGA programming file) and an EDIF (Electronic Design Interchange Format) structural netlist of the hardware annotated with timing information. This netlist can be simulated with the test vectors produced previously from system simulations to verify the performance of the completed FPGA hardware realization.
Application as in FIR Filter:
Thus the above design flow gives the overhead of the design strategy of a FPGA based DSP system. Let us consider a Finite Impulse Response(FIR) filter logic circuit.
In binary arithmetic, multiplication by a power-of-two is simply a shift operation. Implementation of systems with multiplications may be simplified by using only a limited number of power-of-two terms, so that only a limited number of shift and add operations are required. In order to obtain good performance using a small number of such terms, the number of power-of-two terms used in approximating each coefficient value, the architecture of the filter, and the optimization technique used to derive the discrete space coefficient values must be carefully selected. It can be demonstrated that an FIR filter with -60dB of frequency response ripple magnitude can be realized using two power-of-two terms for each coefficient value. An inverted form FIR filter, which can be used in FPGA implementations, is depicted in Figure . If the coefficient value is an integer power-of-two or a sum of two powers-of-two, the multipliers can be replaced by one or two shifters. Since the coefficients will be fixed for this class of filter, the coefficient values can be realized by appropriately routing the inputs to the full adders in the filter structure. That is, moving the adder inputs k places to the left achieves the same effect as
would a coefficient value of 2k.
Conclusion:
This paper has demonstrated a design flow technique that makes the FPGA a viable platform for DSP system engineers to use in implementing DSP algorithms. Future work will provide extensions and refinements to improve quality of result and ease of use, including the following:
- Mapper improvements
- Control logic generation
- Test bench generation
- Library and toolbox development.
- Support for additional system level tools
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